// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  hipciec_nvme_global_reg_reg_offset.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1.0
// Date          :  2017/10/24
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.2 
// History       :  xxx 2018/03/16 18:03:15 Create file
// ******************************************************************************

#ifndef __HIPCIEC_NVME_GLOBAL_REG_REG_OFFSET_H__
#define __HIPCIEC_NVME_GLOBAL_REG_REG_OFFSET_H__

/* HIPCIEC_NVME_GLOBAL_REG Base address of Module's Register */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE                       (0x80300)

/******************************************************************************/
/*                      HiPCIECTRL40V200 HIPCIEC_NVME_GLOBAL_REG Registers' Definitions                            */
/******************************************************************************/

#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_NVME_CTRL_MISC_REG          (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x0)  /* NVMe Local Misc Control */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_SRIOV_MODE_CTRL_REG         (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x4)  /* NVMe SRIOV Mode Control */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_PF0_BAR0_DB_ATU_LOW_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x8)  /* PF0 BAR0 doorbell ATU Register Low */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_PF0_BAR0_DB_ATU_HIGH_REG    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0xC)  /* PF0 BAR0 doorbell ATU Register High */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_PF2_VF_BAR0_DB_ATU_LOW_REG  (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x10) /* PF2 VF BAR0 doorbell ATU Register Low */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_PF2_VF_BAR0_DB_ATU_HIGH_REG (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x14) /* PF2 VF BAR0 doorbell ATU Register High */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_PF3_BAR0_DB_ATU_LOW_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x18) /* PF3 BAR0 doorbell ATU Register Low */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_PF3_BAR0_DB_ATU_HIGH_REG    (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x1C) /* PF3 BAR0 doorbell ATU Register High */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_PF3_VF_BAR0_DB_ATU_LOW_REG  (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x20) /* PF3 VF BAR0 doorbell ATU Register Low */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_PF3_VF_BAR0_DB_ATU_HIGH_REG (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x24) /* PF3 VF BAR0 doorbell ATU Register High */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_INT_COAL_TIME_CNT_UNIT_REG  (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x28) /* Interrupt Coal Timer Count Unit */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_PF0_DB_INT_MASK0_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x2C) /* PF0 Doorbell Interrupt Mask0 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_PF0_DB_INT_MASK1_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x30) /* PF0 Doorbell Interrupt Mask1 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_PF0_DB_INT_MASK2_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x34) /* PF0 Doorbell Interrupt Mask2 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_PF0_DB_INT_MASK3_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x38) /* PF0 Doorbell Interrupt Mask3 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_PF0_DB_INT_PENDING0_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x3C) /* PF0 Doorbell Interrupt Pending0 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_PF0_DB_INT_PENDING1_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x40) /* PF0 Doorbell Interrupt Pending1 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_PF0_DB_INT_PENDING2_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x44) /* PF0 Doorbell Interrupt Pending2 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_PF0_DB_INT_PENDING3_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x48) /* PF0 Doorbell Interrupt Pending3 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_PF3_DB_INT_MASK0_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x4C) /* PF3 Doorbell Interrupt Mask0 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_PF3_DB_INT_MASK1_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x50) /* PF3 Doorbell Interrupt Mask1 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_PF3_DB_INT_MASK2_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x54) /* PF3 Doorbell Interrupt Mask2 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_PF3_DB_INT_MASK3_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x58) /* PF3 Doorbell Interrupt Mask3 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_PF3_DB_INT_PENDING0_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x5C) /* PF3 Doorbell Interrupt Pending0 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_PF3_DB_INT_PENDING1_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x60) /* PF3 Doorbell Interrupt Pending1 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_PF3_DB_INT_PENDING2_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x64) /* PF3 Doorbell Interrupt Pending2 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_PF3_DB_INT_PENDING3_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x68) /* PF3 Doorbell Interrupt Pending3 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_DB_INT_COAL_CFG_REG         (HiPCIECTRL40V200_HIPCIEC_NVME_GLOBAL_REG_BASE + 0x6C) /* Doorbell Interrupt Coal Cfg */

#endif // __HIPCIEC_NVME_GLOBAL_REG_REG_OFFSET_H__
